AMD K5 User Manual

Signal Descriptions 5-103
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.42 PRDY (Probe Ready)
Output
Summary The processor asserts PRDY to acknowledge the system logic’s
assertion of R/S or execution of the Test Access Port (TAP)
instruction, USEHDT, and to indicate the processor’s entry
into the Hardware Debug Tool (HDT) mode for debugging.
Driven The processor drives PRDY every clock in response to either
R/S or the TAP instruction, USEHDT. The processor asserts
PRDY at the next instruction boundary after R/S is sampled
Low or when the USEHDT instruction is executed. The latter
causes the processor to assert PRDY without a transition on
R/S. After PRDY is asserted by either means, the processor
negates PRDY on the later of (a) the clearing of the TAP
instruction register, (b) a TAP reset, or (c) after a Low-to-High
transition on R/S.
PRDY is driven in memory cycles (including writethroughs and
writebacks), cache accesses, and I/O cycles in the normal oper-
ating modes (Real, Protected, and Virtual-8086) and in SMM;
in the Shutdown, Halt or Stop Grant states; or while AHOLD,
BOFF, HLDA, or RESET is asserted. PRDY is not driven dur-
ing locked cycles, special bus cycles, or interrupt acknowledge
operations; during the Stop Clock state; or while INIT is
asserted.
Details The HDT is entered either when external debug logic drives
R/S Low or loads the TAP instruction register with the USE-
HDT instruction. If R/S is used to initiate the HDT, the debug
logic must hold R/S Low throughout the debug session. If the
USEHDT instruction is used to initiate the HDT, the processor
asserts PRDY without a transition on R/S.
The processor negates PRDY and begins fetching instructions
for normal operation one clock after a Low-to-High transition
on R/S, or when the TAP instruction register is cleared, or the
TAP is reset.
Debug software can force the processor into SMM, but the pro-
cessor does not recognize SMI or any other interrupts while
PRDY is asserted. If system hardware or software wishes to
assert RESET, it must exit the HDT before asserting RESET.

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm