2-4 Internal Architecture
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
2.2 Execution Pipeline
Figure 2-1 shows the relation between the internal logic and
the stages of the execution pipeline. Figure 2-2 shows the func-
tions of the pipeline stages. The first five stages—Fetch,
Decode 1, Decode 2, Execute, and Result—affect throughput
performance. The sixth stage, Retire, may occur at a variable
number of clocks after the Result stage, but the Retire stage
does not affect throughput performance when the processor
operates in a non-serialized mode, which is typical of most pro-
cessing. Thus, the pipeline effectively has five stages. Because
the pipeline is moderately shallow, penalties associated with
mispredicting a branch (three clocks) or clearing the pipeline
(variable clocks) are relatively small compared with processors
that have deeper pipelines (more pipeline stages).
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