Bus Cycle Timing 5-169
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.4.5 Locked Cycles
The processor asserts LOCK across certain sequences of mem-
ory bus cycles that require integrity. These include interrupt
acknowledge operations, descriptor-table updates, page-direc-
tory and page-table updates, and exchange operations. In addi-
tion, the processor asserts LOCK during bus cycles initiated by
any instruction that has the LOCK prefix. The processor locks
only memory cycles, not I/O cycles.
LOCK is an indication to system logic that it should maintain
the integrity of the locked bus cycles, either by never interven-
ing in them or by some other system-level memory protection
mechanism that guarantees integrity.
Locked operations generated by the processor typically consist
of a read-write pair of bus cycles with an operand modification
between the two bus cycles (sometimes called read-modify-
write), except that interrupt acknowledge operations, which
are also locked, consist of a pair of read cycles with no operand
modification between the cycles. Locked operations generated
by the LOCK instruction prefix cause LOCK to be asserted
only during bus cycles initiated by that single instruction. The
processor guarantees at least one idle (or dead) clock between
consecutive bus cycles, whether unlocked or locked. This
means that consecutive locked operations, which consist of
consecutive bus cycles, also have at least one idle clock
between them.
Basic Locked
Operation
Figure 5-16 shows a pair of read-write bus cycles. The proces-
sor asserts LOCK with the ADS of the first bus cycle in the
locked operation, and holds it asserted until the last expected
BRDY of the last bus cycle in the locked operation. Between
the locked operations, the processor negates LOCK for at least
one clock.
This example also shows that the value driven on A31–A3 is
valid only during the assertion of ADS. In the clock immedi-
ately preceding the ADS for the write in the first locked opera-
tion, the processor changes the address. If system logic reads
the address in the clock before ADS, an unexpected value may
be returned.
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