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2-20 Internal Architecture

AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996

Table 2-3. Cache States for Snoops, Invalidation, and Replacements

Type of

Operation

Tags

Cache State

Before

Operation

Memory Access

Cache State After Operation

MESI State

Writeback-

Writethrough State

Inquire

Cycle

Physical

shared or exclu-

sive

—

INV=0 shared writethrough

INV=1 invalid invalid

modified

burst write (write-

back)

INV=0 shared writethrough

INV=1 invalid invalid

Internal

Snoop

Physical

shared or exclu-

sive

—

invalid invalid

modified

burst write (write-

back)

FLUSH

Signal

Physical

shared or exclu-

sive

—

invalid invalid

modified

burst write (write-

back)

WBINVD

Instruction

Physical

shared or exclu-

sive

—

invalid invalid

modified

burst write (write-

back)

INVD

Instruction

— — — invalid invalid

Cache-Line

Replacement

Physical

shared or exclu-

sive

—

Depends on

replacement-line

characteristics

modified

burst write (write-

back)

Notes:

1. Linear tags are masked by A20M, physical tags are not.

2. Writeback = 32 bytes.

3. MESI state is stored in the physical tags. Instruction-cache state consists only of valid (shared) or invalid, and there are no write-

related states.

— Not applicable or none.

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AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm