AMD K5

2-20 Internal Architecture
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
Table 2-3. Cache States for Snoops, Invalidation, and Replacements
Type of
Operation
Tags
1
Cache State
Before
Operation
3
Memory Access
3
Cache State After Operation
MESI State
5
Writeback-
Writethrough State
Inquire
Cycle
Physical
shared or exclu-
sive
—
INV=0 shared writethrough
INV=1 invalid invalid
modified
burst write (write-
back)
INV=0 shared writethrough
INV=1 invalid invalid
Internal
Snoop
Physical
shared or exclu-
sive
—
invalid invalid
modified
burst write (write-
back)
FLUSH
Signal
Physical
shared or exclu-
sive
—
invalid invalid
modified
burst write (write-
back)
WBINVD
Instruction
Physical
shared or exclu-
sive
—
invalid invalid
modified
burst write (write-
back)
INVD
Instruction
— — — invalid invalid
Cache-Line
Replacement
Physical
shared or exclu-
sive
—
Depends on
replacement-line
characteristics
modified
burst write (write-
back)
Notes:
1. Linear tags are masked by A20M, physical tags are not.
2. Writeback = 32 bytes.
3. MESI state is stored in the physical tags. Instruction-cache state consists only of valid (shared) or invalid, and there are no write-
related states.
— Not applicable or none.