Signal Descriptions 5-79
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.30 IGNNE (Ignore Numeric Error)
Input
Summary IGNNE, in conjunction with the numeric error (NE) bit in CR0,
is used by the system logic to control the effect of an unmasked
floating-point exception on a previous floating-point instruc-
tion during the execution of a floating-point instruction or the
WAIT instruction—hereafter referred to as the target instruc-
tion.
Sampled The processor samples IGNNE every clock during memory
cycles (including cache writethroughs and writebacks), cache
hits of all types, I/O cycles, locked cycles, special bus cycles,
and interrupt acknowledge operations in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM; or
while AHOLD, BOFF, or HLDA is asserted. IGNNE is not sam-
pled in the Shutdown, Halt, Stop Grant, or Stop Clock states; or
while RESET, INIT, or PRDY is asserted.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously driven setup
and hold times).
Details If an unmasked floating-point exception is pending and the tar-
get instruction is considered error-sensitive, then the relation-
ship between NE and IGNNE is as follows:
■ If NE = 0, then:
• If IGNNE is sampled asserted, the processor ignores the
floating-point exception and continues with the execu-
tion of the target instruction.
• If IGNNE is sampled negated, the processor waits until it
samples IGNNE, INTR, SMI, NMI, or INIT asserted.
If IGNNE is sampled asserted while waiting, the proces-
sor ignores the floating-point exception and continues
with the execution of the target instruction.
If INTR, SMI, NMI, or INIT is sampled asserted while
waiting, the processor handles its assertion appropri-
ately.
■ If NE = 1, the processor invokes the INT 10h exception
handler.
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