AMD K5 User Manual

Signal Descriptions 5-99
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
5.2.39 PCD (Page Cache Disable)
Output
Summary The processor drives PCD to indicate the operating system’s
specification of cacheability for the entire current page. Sys-
tem logic can use PCD to control external caching.
Driven and Floated The processor drives PCD from the clock in which ADS is
asserted until the last expected BRDY of the bus cycle.
PCD is driven during memory cycles (including cache
writethroughs and writebacks) and locked cycles in the normal
operating modes (Real, Protected, and Virtual-8086) and in
SMM. While AHOLD is asserted, PCD is driven only to com-
plete a bus cycle that had been initiated before AHOLD was
asserted. PCD is not driven during special bus cycles, or inter-
rupt acknowledge operations; or in the Shutdown, Halt or Stop
Grant states, except for writebacks due to inquire cycles; and
PCD is never driven during the Stop Clock state, or while
BOFF, HLDA, RESET, INIT, or PRDY is asserted.
The processor floats PCD one clock after system logic asserts
BOFF and in the same clock that the processor asserts HLDA.
Details If PCD is negated during read misses, the page being accessed
may or may not be cacheable, depending on the state of other
signals. If PCD is asserted during any type of access, the page
is noncacheable. The PCD output affects the processor’s cach-
ing of data only during read misses. It has no effect on the pro-
cessor during read hits, write misses, or write hits, as shown in
Tables 5-17 and 5-18 on page 5-135.
The state of the PCD output is a page-level specification of
cacheability based on the state of several bits written by the
operating system. In Protected mode, the PCD output specifies
the cacheability of the entire page being accessed. The bits
that determine the PCD output are stored in one of the proces-
sor’s control registers or its TLB. Those bits include the cache
disable (CD) bit in CR0, the paging enable (PG) bit in CR0, and
the page cache disable (PCD) bit in one of three locations. The
selection of bits depends on the processor’s operating mode
and the type of access, as follows:

AMD K5 Specifications

General

Manufacturer	AMD
Model	K5
Architecture	x86
Microarchitecture	K5
Introduction Year	1996
Clock Speed	75 - 133 MHz
Core Count	1
Socket	Socket 7
Core stepping	SSA/5, 5k86
Voltage	3.3V
Transistors	4.3 million
L1 Cache	8 KB (data) + 16 KB (instruction)
FSB	50 MHz to 66 MHz
Process Technology	350 nm