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AMD K5 User Manual

AMD K5
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3-24 Software Environment and Extensions
AMD-K5 Processor Technical Reference Manual 18524C/0Nov1996
3.1.5 Protected Virtual Interrupt (PVI) Extensions
The Protected Virtual Interrupts (PVI) bit in CR4 enables sup-
port for interrupt virtualization in Protected mode. In this vir-
tualization, the processor maintains program-specific VIF and
VIP flags in a manner similar to those in Virtual-8086 Mode
Extensions (VME). When a program is executed at CPL = 3, it
can set and clear its copy of the VIF flag without causing gen-
eral-protection exceptions.
The only differences between the VME and PVI extensions are
that, in PVI, selective INTn interception using the Interrupt
Redirection Bitmap in the TSS does not apply, and only the STI
and CLI instructions are affected by the extension.
Table 3-5A through Table 3-5E and Table 3-6 show, among
other things, the behavior of hardware and software inter-
rupts, and instructions that affect interrupts, in Protected
mode with the PVI extensions enabled.

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AMD K5 Specifications

General IconGeneral
ManufacturerAMD
ModelK5
Architecturex86
MicroarchitectureK5
Introduction Year1996
Clock Speed75 - 133 MHz
Core Count1
SocketSocket 7
Core steppingSSA/5, 5k86
Voltage3.3V
Transistors4.3 million
L1 Cache8 KB (data) + 16 KB (instruction)
FSB50 MHz to 66 MHz
Process Technology350 nm

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