7-2 Test and Debug
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
■ Test Access Port (TAP) Boundary-Scan Testing—The JTAG
test access functions defined by the IEEE Standard Test
Access Port and Boundary--Scan Architecture (IEEE 1149.1-
1990) specification.
■ Hardware Debug Tool (HDT)—The hardware debug tool
(HDT), sometimes referred to as the debug port or Probe
mode, is a collection of signals, registers, and processor
microcode that is enabled when external debug logic drives
R/S Low or loads the AMD-K5 processor’s Test Access Port
(TAP) instruction register with the USEHDT instruction.
The test-related signals and their descriptions include the fol-
lowing:
■ FLUSH—Page 5-65
■ FRCMC—Page 5-68
■ IERR—Page 5-78
■ INIT—Page 5-81
■ PRDY—Page 5-103
■ R/S—Page 5-107
■ RESET—Page 5-109
■ TCK—Page 5-127
■ TDI—Page 5-128
■ TDO—Page 5-129
■ TMS—Page 5-130
■ TRST—Page 5-131
The sections that follow provide details on each of the test and
debug features.
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