Signal Descriptions 5-61
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
while the TAP instruction, RUNBIST, is executed. The proces-
sor accesses the physical tag array during both BISTs and
inquire cycles via EADS, and these accesses can conflict.
The 486 processor without writeback cache samples EADS in
every clock, including while the processor drives the address
bus. It can thus support inquire cycles every clock. The
AMD-K5 and Pentium processors, by comparison, can sample
EADS every other clock, and the maximum inquire or invalida-
tion rate with inquire cycles is one every two clocks, because
HIT and HITM change state two clocks after EADS, and EADS
can be asserted in the same clock in which HITM is negated.
The AMD-K5 processor does not sample EADS in the clock
after a valid EADS assertion.
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