AMD K5

Signal Overview 5-9
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Cache Control
CACHE
O 38 37 25 25 25 25 16 3 3 3 21
KEN
42
I 16 21
PCD O
38 16 3 3 3 21
PWT O
38 16 3 3 3 15
WB/WT
I 38 16 15
Data and Data Parity
BRDY
I 38 37 16 3 3 3
BRDYC I 38 37 16 3 3 3
D63–D0 I/O 38 37 16 3 3 3
DP7–DP0 I/O 38 37 16 3 3 3
PCHK
42
O 16
PEN
42
I 16
Inquire Cycles
EADS
7
I 43 43 43 43 1 43 43
HIT O 1
HITM O 1
INV I 43 43 43 43 1 43 43
Floating-Point Errors
FERR
O
IGNNE I
Table 5-2. Conditions for Driving and Sampling Signals (continued)
Signal
Conditions under which signals are meaningfully driven or sampled
Bus Cycles or Cache Accesses
38
Arbitration
States and Modes
8
Reset,
Debug
Memory Reads
14
Memory Writes
14
Cache Hits
39
Inquire Cycles
3
I/O Cycles Locked Cycles Special Cycles Interrupt Acknow. AHOLD Active BOFF Active HLDA Active Shutdown
33
Halt Stop Grant Stop Clock SMIACT Active RESET Active INIT Active PRDY Active