5-10 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
External Interrupts, Interrupt Acknowledgments, and Reset
BUSCHK
29
I 38 29 16 3 12 12
FLUSH
27
I 41 41 41 41 12
INIT
27
I 30 30 30 30 12 9 —
INTR
5, 28
I 40 40 40 40
NMI
27
I 12 9
PRDY O
—
R/S
28
I 31
RESET I
30 30 30 30 —17
SMI
27
I 12 22
SMIACT
O — 32
STPCLK
28
I 34 34 34 34 24
Test and Debug
FRCMC
I
IERR O2020202020202020202020202020 202020
PRDY O See “External Interrupts, Interrupt Acknowledgments, and Reset”
R/S
I See “External Interrupts, Interrupt Acknowledgments, and Reset”
TCK I
TDI I
TDO O
TMS I
TRST I
Bus and Processor Clock
BF I 11
BF1–BF0 I 11
CLK I 11
Table 5-2. Conditions for Driving and Sampling Signals (continued)
Signal
Conditions under which signals are meaningfully driven or sampled
Bus Cycles or Cache Accesses
38
Arbitration
States and Modes
8
Reset,
Debug
Memory Reads
14
Memory Writes
14
Cache Hits
39
Inquire Cycles
3
I/O Cycles
Locked Cycles
Special Cycles
Interrupt Acknow.
AHOLD Active
BOFF Active
HLDA Active
Shutdown
33
Halt
Stop Grant
Stop Clock
SMIACT Active
RESET Active
INIT Active
PRDY Active
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