AMD K5

Signal Overview 5-11
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
Notes to Table 5-2:
– Shading indicates signals that are meaningfully driven or sampled. Signals that are not shaded are not driven or sampled or are not
meaningful.
1. Inquire cycles can be driven while LOCK
is asserted if AHOLD is used to obtain the bus for the inquire cycle. Inquire cycles never hit
locations involved in a locked operation because the processor invalidates such locations, if found in the cache, before doing the
locked operation. If the inquire cycle hits a modified location that is different than the one involved in the locked operation, the write-
back may be done in the middle of the locked operation, between the two locked cycles, with LOCK
asserted during the writeback.
2. A31–A5 are I/O signals (input for inquire cycles), but A4–A3 are output only.
3. Sampled or driven during inquire cycles or resulting writebacks.
4. Sampled only during inquire cycles, but not driven for resulting writebacks.
5. If enabled by the IF flag in EFLAGS.
6. Output only.
7. If AHOLD is held asserted throughout an inquire cycle and writeback, system logic must use its latched copy of the inquire cycle
address for the writeback. By contrast, if system logic always negates AHOLD before the writeback, the processor will drive the write-
back address when it asserts ADS
for the writeback.
8. Signal recognition and assertion applies to the actual state, not to the special cycle driven by the processor prior to entering the state.
9. During SMM, NMI and INIT are recognized only in response to an IRET instruction. After the return from SMM (RSM instruction), a
latched NMI or INIT will be serviced.
10. A20M
is recognized only in Real mode, and masking is applied to linear addresses. Because the caches are linearly tagged, assertion
of A20M during Real mode affects all program-generated cache addresses, including cache-line fills (caused by read misses), cache
writethroughs (caused by write misses or write hits to lines in the shared state) and cache accesses that occur while the processor
does not control the bus. However, A20M
does not mask inquire cycle addresses or any writebacks caused by inquire cycles; these
addresses are looked up only in the physical tags, which are not masked by A20M.
11. CLK can be driven with a different frequency, and/or BF can be changed when CLK is restarted on exit from the Stop-Clock state.
12. Latched or (in the case of BUSCHK
) otherwise sampled and held, pending exit from this state.
13. SCYC may be asserted during any misaligned memory or I/O cycle, but it is only meaningful during locked cycles.
14. Includes Protected, Virtual-8086 and Real modes, unless otherwise indicated.
15. During the Hardware Debug Tool (HDT) mode, this signal is only meaningful for cache write misses (PWT=0 and WB/WT
=1 tran-
sition a shared line to an exclusive line). The signal is not meaningful during cache read misses in the HDT mode, because the caches
are never filled during the HDT mode.
16. Sampled or driven only during the completion of a cycle the processor initiated before the assertion of AHOLD, or for writebacks due
to inquire cycles.
17. Different than the Pentium processor. The system hardware or software must exit the HDT before asserting RESET.
18. NA
acts as an assertion of BRDY, but only when sampled with KEN or WB/WT. It is valid only for memory reads and writes, including
writethroughs during cache hits to shared or exclusive lines. NA has no effect on any signals other than KEN and WB/WT, and
addresses are not pipelined when NA
is asserted.
19. If an inquire cycle occurs during a Branch-Trace Message special cycle, the branch address information driven by the processor on
A31–A3 can be overwritten by the inquiring bus master. In such cases, external logic should latch A31–A3 when ADS
is asserted (i.e.,
before asserting AHOLD, BOFF
or HOLD).
20. Used only to report errors in Functional Redundancy Checking mode and driven only by the Checker.
21. This signal is not meaningful during cache read misses in the HDT mode, because the caches are never filled in the HDT mode.
22. The debugger can force the processor into SMM, but the processor will not recognize SMI
until PRDY is negated. If SMI is asserted
while PRDY is asserted, it is latched and acted upon after PRDY is negated.
23. During AHOLD, the system must prevent other bus masters from locking the same address that the AMD-K5 processor is locking.
24. Different than the Pentium processor, which ignores STPCLK
in this state.
25. Always negated (non-cacheable).
26. EWBE
is not checked prior to running special bus cycles or interrupt acknowledge operations. All special bus cycles (which have
W/R
=1) and interrupt acknowledge operations (which have W/R=0) serialize the pipeline and do not require EWBE for this purpose.
27. An edge-triggered interrupt. It is latched when sampled and recognized on an instruction boundary.
28. A level-sensitive interrupt. It must be held asserted until recognized, which occurs on an instruction boundary.
29. Unlike other level-sensitive interrupts, BUSCHK
is sampled with every BRDY and it does not need to be held asserted after sampling.
If BUSCHK is asserted during a locked operation or inquire cycle, an enabled machine-check exception will not be acted upon until
after the last BRDY of the locked operation or after a writeback caused by an inquire cycle.