AMD K5

5-12 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
30. The first code fetch after register initialization during INIT or RESET does not occur if AHOLD, BOFF
, or HLDA is asserted.
31. PRDY is asserted either when R/S
goes Low or when the Test Access Port (TAP) instruction, USEHDT, is executed. In the latter case,
R/S is watched for a Low-to-High transition, which takes the processor out of the Hardware Debug Tool (HDT) mode.
32. The processor can go into the Hardware Debug Tool (HDT) mode from within SMM either when R/S
goes Low or when the TAP
instruction, USEHDT, is executed (the instruction causes the processor to assert PRDY). In this case, SMIACT
can be toggled with HDT
commands. SMIACT selects main or SMM memory.
33. Only NMI, INIT, RESET, and SMI
gets the processor out of the Shutdown state.
34. The processor cannot drive the Stop-Grant special bus cycle.
35. HOLD is sampled, but the only practical effect is to assert HLDA.
36. Writebacks or writethroughs cannot occur when HLDA is asserted.
37. During writebacks.
38. During writebacks or writethroughs.
39. Including writebacks and writethroughs (except for HLDA).
40. The processor cannot drive the interrupt acknowledge cycle, and therefore cannot obtain the interrupt vector.
41. If FLUSH
is asserted while AHOLD, BOFF, or HLDA is asserted, the outcome of the flush depends on whether the flush causes write-
backs of modified lines. If no writebacks are needed, the processor invalidates all lines but does not perform the FLUSH-acknowledge
cycle until the processor gets control of the bus again. If a writeback is needed, the processor stops at that writeback without having
invalidated any lines, waits until control of the bus is returned to the processor, then completes the FLUSH
operation.
42. Driven or sampled only during reads.
43. Sampled after AHOLD or HLDA is asserted, and while the processor completes an in-progress bus cycle.
44. Without ADS
during cache accesses, with ADS during cache writethroughs and writebacks.