5-108 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
2. Acknowledge—The processor asserts PRDY to acknowledge
the interrupt and mark entry into the HDT mode. The pro-
cessor does not save its state before asserting PRDY
because it will continue execution at the next instruction
after returning from the debug session, when R/S and
PRDY are negated.
If R/S is used to initiate the HDT, the debug logic must hold R/
S Low throughout the debug session. The processor negates
PRDY and begins fetching instructions for normal operation
one clock after a Low-to-High transition on R/S, or when the
TAP instruction register is cleared or the TAP is reset.
The processor recognizes AHOLD, BOFF, and HOLD while R/S
is Low, and these signals will intervene in the HDT mode when
PRDY is asserted. However, exceptions or interrupts are not
recognized in the HDT mode. The processor latches the asser-
tion of any edge-triggered interrupt (FLUSH, SMI, INIT, NMI)
during the HDT mode and recognizes them in priority order
when PRDY is negated. See Table 5-3 on page 5-16 for the pri-
ority of interrupts and exceptions.
Documentation on the HDT is available under non-disclosure
agreement to test and debug developers. For information, con-
tact your AMD sales representative or field application engi-
neer.
The AMD-K5 processor implements the HDT mode in a manner
different than the Pentium processor’s Probe mode. For details
on the processor’s PRDY acknowledgment to R/S, see page 5-
103. For details on TAP testing, see Section 7.8 on page 7-19.
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