AMD K5

Signal Descriptions 5-43
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
The assertion of NA acts as an assertion of BRDY only when
the processor samples KEN or WB/WT.
The processor drives or asserts the following outputs relative
to the assertion of BRDY:
■ D63–D0—For single-transfer write cycles, the processor
drives data from one clock after ADS until BRDY is
returned. For burst transfers, the processor drives data
from one clock after ADS until the first BRDY is returned,
and thereafter from each BRDY until the next BRDY.
■ DP7–DP0—Same as D63–D0.
■ PCHK—Two clocks after every BRDY for writes.
In addition to the above uses of BRDY on the 486 processor,
BRDY on the AMD-K5 and Pentium processors is used for both
single-transfer and burst cycles, and it terminates special bus
cycles.
Unlike BRDY on the 486 processor, BRDY on the AMD-K5 and
Pentium processors is used for both single-transfer and burst
cycles, and it terminates special bus cycles. On the 486 proces-
sor, single-transfer cycles and special bus cycles use RDY;
BRDY is used only for burst cycles. The BLAST output on the
486 processor is not implemented on the AMD-K5 and Pentium
processors, which instead use the CACHE output to indicate
cacheability. However, unlike the 486 processor, which can ter-
minate a burst cycle prematurely by negating BLAST, the
AMD-K5 and Pentium processors cannot terminate a burst pre-
maturely.