AMD K5

Dispatch and Execution Timing 4-9
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
BT mem, reg 1_1x_10100011_xxx_xxx M
alu1 1/1
alu 1/2
alu 2/3
ld 2/4
alu1 3/5
BT reg, imm 1_0x_10111010_100_xxx Falu11/1
BT mem, imm 1_1x_10111010_100_xxx F
ld 1/1
alu1 1/2
BTC reg, reg 1_0x_10111011_xxx_xxx Falu11/1
BTC mem, reg 1_1x_10111011_xxx_xxx M
alu1 1/1
alu 1/2
alu 2/3
ld 2/4
alu1 3/5
st 3/5/6
BTC reg, imm 1_0x_10111010_111_xxx Falu11/1
BTC mem, imm 1_1x_10111010_111_xxx F
ld 1/1
alu1 1/2
st 1/1/3
BTR reg, reg 1_0x_10110011_xxx_xxx Falu11/1
BTR mem, reg 1_1x_10110011_xxx_xxx M
alu1 1/1
alu 1/2
alu 2/3
ld 2/4
alu1 3/5
st 3/5/6
BTR reg, imm 1_0x_10111010_110_xxx Falu11/1
BTR mem, imm 1_1x_10111010_110_xxx F
ld 1/1
alu1 1/2
st 1/1/3
BTS reg, reg 1_0x_10101011_xxx_xxx Falu11/1
BTS mem, reg 1_1x_10101011_xxx_xxx M
alu1 1/1
alu 1/2
alu 2/3
ld 2/4
alu1 3/5
st 3/5/6
BTS reg, imm 1_0x_10111010_101_xxx Falu11/1
Table 4-1. Integer Instructions (continued)
Instruction Mnemonic Opcode Format
Fastpath or
Microcode
Execution
Unit Timing