4-10 Performance
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
BTS mem, imm 1_1x_10111010_101_xxx F
ld 1/1
alu1 1/2
st 1/1/3
CALL near relative 0_xx_11101000_xxx_xxx M
alu 1/1
st 1/1/2
alu 1/1
brn 1/1
CALL near reg 0_0x_11111111_010_xxx M
alu 1/1
st 1/1/2
alu 1/1
brn 1/1
CALL near mem 0_1x_11111111_010_xxx M
alu 1/1
ld 1/1
st 1/1/2
alu 1/1
brn 2/2
CBW/DE 0_xx_10011000_xxx_xxx Falu11/1
CMP reg, reg 0_0x_001110xx_xxx_xxx Falu1/1
CMP reg, mem 0_1x_0011101x_xxx_xxx F
ld 1/1
alu 1/2
CMP mem, reg 0_1x_0011100x_xxx_xxx F
ld 1/1
alu 1/2
CMP AL/AX/EAX, imm 0_xx_0011110x_xxx_xxx Falu1/1
CMP reg, imm 0_0x_100000xx_111_xxx Falu 1/1
CMP mem, imm 0_1x_100000xx_111_xxx F
ld 1/1
alu 1/2
CWD/DQ 0_xx_10011001_xxx_xxx Falu11/1
DEC reg 0_xx_01001xxx_xxx_xxx Falu1/1
DEC reg 0_0x_1111111x_001_xxx Falu1/1
DEC mem 0_1x_1111111x_001_xxx F
ld 1/1
alu 1/2
st 1/1/3
IMUL AX, AL, reg 0_0x_11110110_101_xxx F
fpfill 1/1/4
fmul 1/1/4
IMUL EDX:EAX, EAX, reg 0_0x_11110111_101_xxx F
fpfill 1/1/4
fmul 1/1/4
IMUL reg, reg 1_0x_10101111_xxx_xxx F
fpfill 1/1/4
fmul 1/1/4
Table 4-1. Integer Instructions (continued)
Instruction Mnemonic Opcode Format
Fastpath or
Microcode
Execution
Unit Timing