ST STM32G471 User Manual

High-resolution timer (HRTIM) RM0440
1036/2126 RM0440 Rev 4
27.5.54 HRTIM interrupt clear register (HRTIM_ICR)
Address offset: 0x38C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BMPE
RC
DLL
RDYC
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1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. FLT6C
SYSFL
TC
FLT5C FLT4C FLT3C FLT2C FLT1C
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Bits 31:18 Reserved, must be kept at reset value.
Bit 17 BMPERC: Burst mode period flag clear
Writing 1 to this bit clears the BMPER flag in HRTIM_ISR register.
Bit 16 DLLRDYC: DLL Ready Interrupt flag Clear
Writing 1 to this bit clears the DLLRDY flag in HRTIM_ISR register.
Bits 15:7 Reserved, must be kept at reset value.
Bit 6 FLT6C: Fault 6 interrupt flag clear
Writing 1 to this bit clears the FLT6 flag in HRTIM_ISR register.
Bit 5 SYSFLTC: System fault interrupt flag clear
Writing 1 to this bit clears the SYSFLT flag in HRTIM_ISR register.
Bit 4 FLT5C: Fault 5 interrupt flag clear
Writing 1 to this bit clears the FLT5 flag in HRTIM_ISR register.
Bit 3 FLT4C: Fault 4 interrupt flag clear
Writing 1 to this bit clears the FLT4 flag in HRTIM_ISR register.
Bit 2 FLT3C: Fault 3 interrupt flag clear
Writing 1 to this bit clears the FLT3 flag in HRTIM_ISR register.
Bit 1 FLT2C: Fault 2 interrupt flag clear
Writing 1 to this bit clears the FLT2 flag in HRTIM_ISR register.
Bit 0 FLT1C: Fault 1 interrupt flag clear
Writing 1 to this bit clears the FLT1 flag in HRTIM_ISR register.

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English