ST STM32G471 User Manual

RM0440 Rev 4 1039/2126
RM0440 High-resolution timer (HRTIM)
1083
27.5.57 HRTIM output disable register (HRTIM_ODISR)
Address offset: 0x398
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res.
TF2
ODIS
TF1
ODIS
TE2
ODIS
TE1
ODIS
TD2
ODIS
TD1
ODIS
TC2
ODIS
TC1
ODIS
TB2
ODIS
TB1
ODIS
TA2
OD
IS
TA1
OD
IS
wwwwwwwwwwww
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 TF2ODIS: Timer F output 2 disable
Refer to TA1ODIS description.
Bit 10 TF1ODIS: Timer F output 1 disable
Refer to TA1ODIS description
Bit 9 TE2ODIS: Timer E output 2 disable
Refer to TA1ODIS description.
Bit 8 TE1ODIS: Timer E output 1 disable
Refer to TA1ODIS description.
Bit 7 TD2ODIS: Timer D output 2 disable
Refer to TA1ODIS description.
Bit 6 TD1ODIS: Timer D output 1 disable
Refer to TA1ODIS description.
Bit 5 TC2ODIS: Timer C output 2 disable
Refer to TA1ODIS description.
Bit 4 TC1ODIS: Timer C output 1 disable
Refer to TA1ODIS description.
Bit 3 TB2ODIS: Timer B output 2 disable
Refer to TA1ODIS description.
Bit 2 TB1ODIS: Timer B output 1 disable
Refer to TA1ODIS description.
Bit 1 TA2ODIS: Timer A output 2 disable
Refer to TA1ODIS description.
Bit 0 TA1ODIS: Timer A output 1 disable
Setting this bit disables the timer A output 1. The output enters the idle state, either from the run state
or from the fault state.
Writing “0” has no effect.

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English