ST STM32G471 User Manual

High-resolution timer (HRTIM) RM0440
1040/2126 RM0440 Rev 4
27.5.58 HRTIM output disable status register (HRTIM_ODSR)
Address offset: 0x39C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res.
TF2
ODS
TF1
ODS
TE2
ODS
TE1
ODS
TD2
ODS
TD1
ODS
TC2
ODS
TC1
ODS
TB2
ODS
TB1
ODS
TA2
ODS
TA1
ODS
rrrrrrrrrrrr
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 TF2ODS: Timer F output 2 disable status
Refer to TA1ODS description.
Bit 10 TF1ODS: Timer F output 1 disable status
Refer to TA1ODS description.
Bit 9 TE2ODS: Timer E output 2 disable status
Refer to TA1ODS description.
Bit 8 TE1ODS: Timer E output 1 disable status
Refer to TA1ODS description.
Bit 7 TD2ODS: Timer D output 2 disable status
Refer to TA1ODS description.
Bit 6 TD1ODS: Timer D output 1 disable status
Refer to TA1ODS description.
Bit 5 TC2ODS: Timer C output 2 disable status
Refer to TA1ODS description.
Bit 4 TC1ODS: Timer C output 1 disable status
Refer to TA1ODS description.
Bit 3 TB2ODS: Timer B output 2 disable status
Refer to TA1ODS description.
Bit 2 TB1ODS: Timer B output 1 disable status
Refer to TA1ODS description.
Bit 1 TA2ODS: Timer A output 2 disable status
Refer to TA1ODS description.
Bit 0 TA1ODS: Timer A output 1 disable status
Reading the bit returns the output disable status. It is not significant when the output is active
(Tx1OEN or Tx2OEN = 1).
0: Output A1 disabled, in Idle state.
1: Output A1 disabled, in fault state.

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English