ST STM32G471 User Manual

RM0440 Rev 4 1335/2126
RM0440 General-purpose timers (TIM2/TIM3/TIM4/TIM5)
1343
29.5.25 TIMx timer encoder control register (TIMx_ECR)(x = 2 to 5)
Address offset: 0x058
Reset value: 0x0000 0000
Bits 31:0 CCR4[31:0]: Capture/compare 4 value
If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is
loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit
OC4PE). Else the preload value is copied in the active capture/compare 4 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on tim_oc4 output.
Non-dithering mode (DITHEN = 0)
The register holds the compare value.
Dithering mode (DITHEN = 1)
The register holds the integer part in CCR4[31:4]. The CCR4[3:0] bitfield contains the
dithered part.
If channel CC4 is configured as input:
CCR4 is the counter value transferred by the last input capture 4 event (tim_ic4). The
TIMx_CCR4 register is read-only and cannot be programmed.
Non-dithering mode (DITHEN = 0)
The register holds the capture value.
Dithering mode (DITHEN = 1)
The register holds the capture in CCR4[31:0]. The CCR4[3:0] bits are reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. PWPRSC[2:0] PW[7:0]
rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. IPOS[1:0] FIDX Res. Res. IDIR[1:0] IE
rw rw rw rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:24 PWPRSC[2:0]: Pulse width prescaler
This bitfield sets the clock prescaler for the pulse generator, as following:
t
PWG
= (2
(PWPRSC[2:0])
) x t
tim_ker_ck
Bits 23:16 PW[7:0]: Pulse width
This bitfield defines the pulse duration, as following:
t
PW
= PW[7:0] x t
PWG
Bits 15:8 Reserved, must be kept at reset value.

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English