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AES hardware accelerator (AES) RM0440

1532/2126 RM0440 Rev 4

34.7.5 AES key register 0 (AES_KEYR0)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:0 DOUT[31:0]: Output data word

This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon

the computation completion (CCF set), virtually reads a complete 128-bit block of output data from

the AES peripheral. Before reaching the output buffer, the data produced by the AES core are

handled by the data swap block according to the DATATYPE[1:0] bitfield.

Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0].

The data signification of the output data block depends on the AES operating mode:

- Mode 1 (encryption): ciphertext

- Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output)

- Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext

The data swap operation is described in Section 34.4.13: AES data registers and data swapping on

page 1521.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

KEY[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

1514131211109876543210

KEY[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[31:0]: Cryptographic key, bits [31:0]

This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the

operating mode:

- In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single

decryption): the value to write into the bitfield is the encryption key.

- In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before

being used for decryption. After writing the encryption key into the bitfield, its reading before

enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set

returns the decryption key derived from the encryption key.

Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption

key.

The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES

peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly

loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set).

Refer to Section 34.4.14: AES key registers on page 1523 for more details.

ST STM32G471 User Manual

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