RM0440 Rev 4 1713/2126
RM0440 Low-power universal asynchronous receiver transmitter (LPUART)
1733
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 FIFOEN:FIFO mode enable
This bit is set and cleared by software.
0: FIFO mode is disabled.
1: FIFO mode is enabled.
Bit 28 M1: Word length
This bit must be used in conjunction with bit 12 (M0) to determine the word length. It is set or
cleared by software.
M[1:0] = ‘00’: 1 Start bit, 8 Data bits, n Stop bit
M[1:0] = ‘01’: 1 Start bit, 9 Data bits, n Stop bit
M[1:0] = ‘10’: 1 Start bit, 7 Data bits, n Stop bit
This bit can only be written when the LPUART is disabled (UE=0).
Note: In 7-bit data length mode, the Smartcard mode, LIN master mode and Auto baud rate
(0x7F and 0x55 frames detection) are not supported.
Bits 27:26 Reserved, must be kept at reset value.
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in lpuart_ker_ck clock cycles. For more
details, refer Section 37.5.20: RS232 Hardware flow control and RS485 Driver Enable.
This bitfield can only be written when the LPUART is disabled (UE=0).
Bits 20:16 DEDT[4:0]: Driver Enable deassertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal.It is expressed in
lpuart_ker_ck clock cycles. For more details, refer Section 38.4.13: RS232 Hardware flow
control and RS485 Driver Enable.
If the LPUART_TDR register is written during the DEDT time, the new data is transmitted
only when the DEDT and DEAT times have both elapsed.
This bitfield can only be written when the LPUART is disabled (UE=0).
Bit 15 Reserved, must be kept at reset value.
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register.
Bit 13 MME: Mute mode enable
This bit activates the Mute mode function of the LPUART. When set, the LPUART can switch
between the active and Mute modes, as defined by the WAKE bit. It is set and cleared by
software.
0: Receiver in active mode permanently
1: Receiver can switch between Mute mode and active mode.
Bit 12 M0: Word length
This bit is used in conjunction with bit 28 (M1) to determine the word length. It is set or
cleared by software (refer to bit 28 (M1) description).
This bit can only be written when the LPUART is disabled (UE=0).
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