ST STM32G471

RM0440 Rev 4 2081/2126
RM0440 Debug support (DBG)
2112
The Arm
®
Cortex
®
-M4 with FPU core provides integrated on-chip debug support. It is
comprised of:
• SWJ-DP: Serial wire / JTAG debug port
• AHP-AP: AHB access port
• ITM: Instrumentation trace macrocell
• FPB: Flash patch breakpoint
• DWT: Data watchpoint trigger
• TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
• ETM: Embedded Trace Macrocell (available only on STM32G4 Series devices larger
packages, where the corresponding pins are mapped)
It also includes debug features dedicated to the STM32G4 Series:
• Flexible debug pinout assignment
• MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the Arm
®
Cortex
®
-M4 with FPU
core, refer to the Cortex
®
-M4 with FPU-r0p1 Technical Reference Manual and to the
CoreSight Design Kit-r0p1 TRM (see Section 47.2: Reference Arm® documentation).
47.2 Reference Arm
®
documentation
• Cortex
®
-M4 with FPU r0p1 Technical Reference Manual (TRM),
search for “Cortex
®
-M4 with FPU Technical Reference Manual” at
http://infocenter.arm.com
• Arm
®
Debug Interface V5
• Arm
®
CoreSight Design Kit revision r0p1 Technical Reference Manual
47.3 SWJ debug port (serial wire and JTAG)
The STM32G4 Series core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an
Arm
®
standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a
SW-DP (2-pin) interface.
• The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
• The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.