ST STM32G471 User Manual

RM0440 Rev 4 2119/2126
RM0440 Revision history
2119
15-Apr-2020 4
Embedded Flash memory (FLASH) section:
Updated number of wait states for VCORE Range 2 in:
– Table 9: Number of wait states according to CPU clock (HCLK) frequency.
– Table 19: Number of wait states according to CPU clock (HCLK) frequency.
– Table 29: Number of wait states according to CPU clock (HCLK) frequency.
Updated BOOT_LOCK description for the three categories in:
– Section 3.4.1: Option bytes description, Section 4.4.1: Option bytes description,
Section 5.4.1: Option bytes description.
– Section 3.7.17: Flash Securable area bank1 register (FLASH_SEC1R),
Section 4.7.13: Flash Securable area register (FLASH_SEC1R), Section 5.7.13:
Flash Securable area register (FLASH_SEC1R).
Reset and clock control (RCC) section:
Updated:
– Section 7.2.4: PLL.
– Section 7.2.5: LSE clock PLLN[6:0] and PLLM[3:0] description.
High-resolution timer (HRTIM) section:
Updated Section 27.3.1: General description.
Table 447. Document revision history (continued)
Date Revision Changes

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English