Revision history RM0440
2118/2126 RM0440 Rev 4
06-Apr-2020
3
(continued)
DMA request multiplexer (DMAMUX) section:
– Updated Section 13.3.2: DMAMUX mapping.
Analog digital converter (ADC) section:
Updated:
– Section 21.2: ADC main features.
– Figure 83: ADC clock scheme.
– Figure 86: ADC3 connectivity.
– Section 21.4.7: Single-ended and differential input channels.
Comparator (COMP) section:
Updated Figure 168: Comparator block diagram.
Operational amplifier (OPAMP) section:
Updated:
– Table 200: Operational amplifier possible connection.
– Section 25.3.7: Calibration procedure.
– Section 25.3.8: Timer controlled Multiplexer mode procedure.
– Section 25.5.1: OPAMP1 control/status register (OPAMP1_CSR).
– Section 25.5.2: OPAMP2 control/status register (OPAMP2_CSR).
– Section 25.5.3: OPAMP3 control/status register (OPAMP3_CSR).
– Section 25.5.4: OPAMP4 control/status register (OPAMP4_CSR).
– Section 25.5.5: OPAMP5 control/status register (OPAMP5_CSR).
– Section 25.5.6: OPAMP6 control/status register (OPAMP6_CSR).
Advanced-control timers (TIM1/TIM8/TIM20) section:
Updated:
– Section 28.6.27: TIMx alternate function option register 1 (TIMx_AF1)(x = 1, 8, 20).
– Section 28.6.28: TIMx alternate function register 2 (TIMx_AF2)(x = 1, 8, 20).
FD controller area network (FDCAN) section:
Updated Section 44.4.7: FDCAN nominal bit timing and prescaler register
(FDCAN_NBTP) note.
Debug support (DBG) section:
Updated:
– Section 47.4.3: Internal pull-up and pull-down on JTAG pins.
– Section 47.6.1: MCU device ID code.
– Section 47.6.2: Boundary scan TAP.
Device electronic signature section:
– Added Section 48.3: Package data register.
Table 447. Document revision history (continued)
Date Revision Changes
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