ST STM32G471 User Manual

RM0440 Rev 4 225/2126
RM0440 Embedded Flash memory (FLASH) for category 2 devices
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5.7.12 Flash WRP area B address register (FLASH_WRP1BR)
Address offset: 0x30
Reset value: 0x00XX 00XX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
5.7.13 Flash Securable area register (FLASH_SEC1R)
Address offset: 0x70
Reset value: 0xFFFX FFXX
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
Bits 21:16 WRP1A_END: WRP first area “A” end offset
WRP1A_END contains the last page of WRP first area.
Bits 15:6 Reserved, must be kept cleared
Bits 5:0 WRP1A_STRT: WRP first area “A” start offset
WRP1A_STRT contains the first page of WRP first area.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_END[5:0]
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_STRT[5:0]
rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept cleared
Bits 22:16 WRP1B_END: WRP second area “B” end offset
WRP1B_END contains the last page of the WRP second area.
Bits 15:7 Reserved, must be kept cleared
Bits 6:0 WRP1B_STRT: WRP second area “B” start offset
WRP1B_STRT contains the last page of the WRP second area.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BOOT_
LOCK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. SEC_SIZE1
rw rw rw rw rw rw rw rw

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English