ST STM32G471 User Manual

Reset and clock control (RCC) RM0440
308/2126 RM0440 Rev 4
7.4.14 AHB1 peripheral clock enable register (RCC_AHB1ENR)
Address offset: 0x48
Reset value: 0x0000 0100
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG + COMP + OPAMP + VREFBUF reset
0: No effect
1: Reset SYSCFG + COMP + OPAMP + VREFBUF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. CRCEN Res. Res. Res.
FLASH
EN
Res. Res. Res.
FMAC
EN
CORDIC
EN
DMAM
UX1EN
DMA2
EN
DMA1
EN
rw rw rw rw rw rw rw
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disable
1: CRC clock enable
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHEN: Flash memory interface clock enable
Set and cleared by software. This bit can be disabled only when the Flash is in power down
mode.
0: Flash memory interface clock disable
1: Flash memory interface clock enable
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 FMACEN: FMAC enable
Set and reset by software.
0: FMAC clock disabled
1: FMAC clock enabled
Bit 3 CORDICEN: CORDIC clock enable
Set and reset by software.
0: CORDIC clock disabled
1: CORDIC clock enabled

ST STM32G471 Specifications

General

Brand	ST
Model	STM32G471
Category	Microcontrollers
Language	English