Operational amplifiers (OPAMP) RM0440
788/2126 RM0440 Rev 4
OPAMP2_VOUT PA6
ADC2_IN3
ADC2_IN16
(1)
The pin is connected when the OPAMP is
enabled and OPAMP internal output is
disabled. The ADC input is controlled by ADC
OPAMP3_VINM
PB2 (VINM0)
PB10 (VINM1)
OPAMP3_VOUT or PGA controlled by bits PGA_GAIN and VM_SEL
OPAMP3_VINP
PB0 (VINP0)
PB13 (VINP1)
PA1 (VINP2)
DAC3_CH2 controlled by bit VP_SEL
OPAMP3_VOUT PB1
ADC3_IN1/ADC1_IN12
ADC2_IN18
(1)
/ADC3_IN13
(1)
The pin is connected when the OPAMP is
enabled and OPAMP internal output is
disabled. The ADC input is controlled by ADC
OPAMP4_VINM
PB10 (VINM0)
OPAMP4_VOUT or PGA
controlled by bits PGA_GAIN
and VM_SEL
PD8 (VINM1)
OPAMP4_VINP
PB13 (VINP0)
PD11 (VINP1)
PB11 (VINP2)
DAC4_CH1 controlled by bit VP_SEL
OPAMP4_VOUT PB12
ADC4_IN3/ADC1_IN11
ADC5_IN5
(1)
The pin is connected when the OPAMP is
enabled and OPAMP internal output is
disabled. The ADC input is controlled by ADC.
OPAMP5_VINM
PB15 (VINM0)
PA3 (VINM1)
OPAMP5_VOUT or PGA controlled by bits PGA_GAIN and VM_SEL.
OPAMP5_VINP
PB14 (VINP0)
PD12 (VINP1)
PC3 (VINP2)
DAC4_CH2 controlled by bit VP_SEL.
OPAMP5_VOUT PA8
ADC5_IN1
ADC5_IN3
(1)
The pin is connected when the OPAMP is
enabled and OPAMP internal output is
disabled. The ADC input is controlled by ADC.
OPAMP6_VINM
PA1 (VINM0)
PB1 (VINM1)
OPAMP6_VOUT or PGA
controlled by bits PGA_GAIN
and VM_SEL.
OPAMP6_VINP
PB12 (VINP0)
PD9 (VINP1)
PB13 (VINP2)
DAC3_CH1 controlled by bit VP_SEL.
OPAMP6_VOUT PB11
ADC12_IN14
ADC4_IN17
(1)(2)
ADC3_IN17
(1)(3)
The pin is connected when the OPAMP is
enabled and OPAMP internal output is
disabled. The ADC input is controlled by ADC.
1. This ADC channel is connected internally to the OPAMPx_VOUT when OPAINTOEN bit is set. In this case, the I/O on which
the OPAMPx_VOUT is available, can be used for another purpose
2. For category 3 devices only.
3. For category 4 devices only.
Table 200. Operational amplifier possible connection (continued)
Signal Pin Internal Comment
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