High-resolution timer (HRTIM) RM0440
976/2126 RM0440 Rev 4
Bit 16 CPPSTAT: Current push-pull status
This status bit indicates on which output the signal is currently applied, in push-pull mode. It is only
significant in this configuration.
0: Signal applied on output 1 and output 2 forced inactive
1: Signal applied on output 2 and output 1 forced inactive
Bit 15 Reserved, must be kept at reset value.
Bit 14 DLYPRT: Delayed protection flag
0: No delayed protection interrupt occured
1: Delayed Idle or balanced Idle mode entry occured
Bit 13 RST: Reset and/or roll-over interrupt flag
This bit is set by hardware when the timer x counter is reset or rolls over in continuous mode.
0: No TIMx counter reset/roll-over interrupt occurred
1: TIMX counter reset/roll-over interrupt occurred
Bit 12 RSTx2: Output 2 reset interrupt flag
Refer to RSTx1 description
Bit 11 SETx2: Output 2 set interrupt flag
Refer to SETx1 description
Bit 10 RSTx1: Output 1 reset interrupt flag
This bit is set by hardware when the Tx1 output is reset (goes from active to inactive mode).
0: No Tx1 output reset interrupt occurred
1: Tx1 output reset interrupt occurred
Bit 9 SETx1: Output 1 set interrupt flag
This bit is set by hardware when the Tx1 output is set (goes from inactive to active mode).
0: No Tx1 output set interrupt occurred
1: Tx1 output set interrupt occurred
Bit 8 CPT2: Capture 2 interrupt flag
Refer to CPT1 description
Bit 7 CPT1: Capture 1 interrupt flag
This bit is set by hardware when the timer x capture 1 event occurs.
0: No timer x capture 1 interrupt occurred
1: Timer x capture 1 interrupt occurred
Bit 6 UPD: Update interrupt flag
This bit is set by hardware when the timer x update event occurs.
0: No timer x update interrupt occurred
1: Timer x update interrupt occurred
Bit 5 Reserved, must be kept at reset value.
Bit 4 REP: Repetition interrupt flag
This bit is set by hardware when the timer x repetition period has elapsed.
0: No timer x repetition interrupt occurred
1: Timer x repetition interrupt occurred
Bit 3 CMP4: Compare 4 interrupt flag
Refer to CMP1 description
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