RM0440 Rev 4 977/2126
RM0440 High-resolution timer (HRTIM)
1083
27.5.14 HRTIM timer x interrupt clear register (HRTIM_TIMxICR) (x = A to F)
Address offset: Block A: 0x088
Address offset: Block B: 0x108
Address offset: Block C: 0x188
Address offset: Block D: 0x208
Address offset: Block E: 0x288
Address offset: Block F: 0x308
Reset value: 0x0000 0000
Bit 2 CMP3: Compare 3 interrupt flag
Refer to CMP1 description
Bit 1 CMP2: Compare 2 interrupt flag
Refer to CMP1 description
Bit 0 CMP1: Compare 1 interrupt flag
This bit is set by hardware when the timer x counter matches the value programmed in the
compare 1 register.
0: No compare 1 interrupt occurred
1: Compare 1 interrupt occurred
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res.
DLYPR
TC
RSTC
RSTx2
C
SET2x
C
RSTx1
C
SET1x
C
CPT2C CPT1C UPDC Res. REPC CMP4C CMP3C CMP2C CMP1C
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Bits 31:15 Reserved, must be kept at reset value.
Bit 14 DLYPRTC: Delayed protection flag clear
Writing 1 to this bit clears the DLYPRT flag in HRTIM_TIMxISR register
Bit 13 RSTC: Reset interrupt flag clear
Writing 1 to this bit clears the RST flag in HRTIM_TIMxISR register
Bit 12 RSTx2C: Output 2 reset flag clear
Writing 1 to this bit clears the RSTx2 flag in HRTIM_TIMxISR register
Bit 11 SETx2C: Output 2 set flag clear
Writing 1 to this bit clears the SETx2 flag in HRTIM_TIMxISR register
Bit 10 RSTx1C: Output 1 reset flag clear
Writing 1 to this bit clears the RSTx1 flag in HRTIM_TIMxISR register
Bit 9 SETx1C: Output 1 set flag clear
Writing 1 to this bit clears the SETx1 flag in HRTIM_TIMxISR register
Bit 8 CPT2C: Capture 2 interrupt flag clear
Writing 1 to this bit clears the CPT2 flag in HRTIM_TIMxISR register
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