5-82 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
writes to a port (such as port 64h in the keyboard controller)
that asserts INIT.
INIT is also used to support 286 software that must return to
Real mode after accessing extended memory in Protected
mode. The 286 processor does not have an INIT input; a transi-
tion from Protected mode to Real mode can only be made on
the 286 processor by asserting RESET. With the INIT signal,
however, the operating system, through a BIOS interrupt, can
cause the transition without loss of cache contents or floating-
point state.
Upon recognizing an INIT interrupt at the next instruction
retirement boundary, the processor performs the following
actions, in the order shown:
1. Flush Pipeline—The processor invalidates the:
• Instruction pipeline
• Translation look-aside buffer (TLB)
2. Reinitialize—The processor reinitializes the following
resources to reset values:
• General-purpose registers
• System registers
3. Jump To BIOS—The processor jumps to the BIOS at address
FFFF_FFF0h, the same entry point used after RESET. (See
the description of RESET on page 5-109 for details on the
aliasing of this boot address.)
Unlike RESET, INIT does not reinitialize the data and instruc-
tion caches, floating-point registers, model-specific registers,
or cache disable (CD) and not-writethrough (NW) bits in CR0.
A20M should not be asserted during the first code fetch follow-
ing the INIT cycle. The operating system alone is responsible
for controlling the state of A20M by writing to an external reg-
ister provided for this purpose. (See the description of A20M
on page 5-18.)
INIT can only be driven at a predictable time, relative to pro-
gram order, by using an I/O write. Due to the signal’s recogni-
tion on an instruction boundary, if initialization is to be
performed immediately after an I/O write, INIT must be held
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