AMD K5

5-118 Bus Interface
AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996
not SMM memory) before address decoding switches memory
references to the SMM memory space. If no bus cycle is in
progress when SMI is asserted, or if the system does not imple-
ment external write buffers, system logic may assert EWBE at
the same time as SMI or at some later time. If a bus cycle is in
progress when SMI is asserted, EWBE must be asserted with
the last expected BRDY or later.
The default physical location for the 64-Kbyte SMM memory
area is between 0003_0000h and 0003_FFFFh, of which a mini-
mum 32-Kbyte region between 0003_8000h and 0003_FFFFh
must be populated with RAM. The memory controller normally
uses the processor’s assertion of SMIACT to enable SMM mem-
ory. The BIOS and system logic typically remap the SMM mem-
ory area from its default location in low memory to high or
extended memory. System logic must ensure that, during
SMM, all memory accesses are to this SMM memory area or a
remapped location.
In general, system designs that do not overlap the address
space of SMM memory and main memory are simpler and may
perform better. However, if SMM memory space overlaps main
memory space that is cacheable, FLUSH must be asserted
when SMI is asserted so that memory accesses in SMM do not
hit locations cached from main memory. The FLUSH is per-
formed first, because it is a higher-priority interrupt.
If SMM memory is to be cacheable, FLUSH should also be
asserted with SMI when entering SMM, and the SMM service
routine should execute the WBINVD instruction to invalidate
the caches when leaving SMM, just prior to executing the RSM
instruction. If SMM memory is to be noncacheable, KEN must
be negated when FLUSH and SMI are asserted.
SMM addresses and operands default to 16 bits, addresses are
translated in the same manner as in Real mode, and the full 4
Gbytes can be accessed without a segment limit violation.
Unlike the Pentium processor, the AMD-K5 processor does not
recognize A20M in SMM. The processor exits SMM (that is, the
SMM service routine) when it executes the RSM instruction.
This instruction causes the processor to copy the contents of
the SMM state-save area into the processor’s registers and
flush the instruction pipeline. Then, the processor continues
executing instructions at the location specified by the CS:EIP
value from the state-save area (which will be where the proces-