AMD K5

Signal Descriptions 5-123
18524C/0—Nov1996 AMD-K5 Processor Technical Reference Manual
relevant information and decide to power itself (the processor)
down, and the decision would be communicated to the power
management logic, which would assert STPCLK to the proces-
sor and, optionally, stop driving CLK to the processor and
other logic.
Upon recognizing a STPCLK interrupt at the next instruction
retirement boundary, the processor performs the following
actions, in the order shown:
1. Flush Pipeline—The processor invalidates all instructions
remaining in the pipeline.
2. Complete In-Progress Cycle—If the processor had begun a
bus cycle or locked operation when STPCLK was asserted,
the processor completes the bus cycle and waits until the
system asserts the last expected BRDY and also asserts
EWBE. If no bus cycle is in progress, system logic must
assert EWBE at the same time or at some time after it
asserts STPCLK.
3. Acknowledge—After sampling both EWBE asserted, the pro-
cessor drives a Stop Grant special bus cycle. This cycle is
identified by D/C = 0, M/IO = 0, W/R = 1, BE7–BE0 = FBh
and A31–A3 = 10h. System logic must respond with BRDY.
4. Stop Internal Clock—When system logic returns BRDY for
the Stop Grant special bus cycle, the processor stops its
internal clock and floats D63–D0 and DP7–DP0.
5. (Optional) Stop Bus Clock—After returning BRDY in
response to the Stop Grant special bus cycle, power man-
agement logic can transition to the Stop Clock state by stop-
ping CLK while STPCLK is held asserted. This reduces
power consumption to its minimum.
STPCLK must be held asserted throughout the Stop Grant and
(if entered) Stop Clock states. Within less than 10 clocks after
STPCLK is negated, the processor returns to the state from
which it entered Stop Grant and can recognize any latched
interrupts or drive ADS.
The processor enters the Halt state from the normal operating
modes (Real, Protected or Virtual-8086) or SMM when it exe-
cutes the HLT instruction. The processor leaves the Halt state
and returns to its prior operating mode when RESET, SMI,
INIT, NMI, or INTR is asserted. If STPCLK is asserted within