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4-6 Performance

AMD-K5 Processor Technical Reference Manual 18524C/0—Nov1996

The second column contains an identifier with the following

format:

The third column in the tables indicates whether the instruc-

tion is Fastpath (F) or Microcoded (M). Fastpath and MROM

ROPs cannot both be present in a decode stage at the same

time. If a microcoded instruction appears at the head of the

byte queue without having been present in the queue on the

previous cycle, there is a one-cycle penalty for MROM entry

point generation.

Each x86 instruction is converted into one or more ROPs. The

fourth column shows the execution unit and timing for each of

the ROPs. The ROP types and corresponding execution units

are:

■ ld—load/store

■ st—load/store

■ alu—either alu0 or alu1

■ alu0—alu0 only

■ alu1—alu1 only

■ brn—branch

■ fadd—floating-point add pipe

■ fmul—floating-point multiply pipe

■ fpmv—floating-point move and compare pipe

■ fpfill—floating-point upper half

MODrm[2:0]

1 = two-byte opcode (0F xx)

MODrm[5:3]

Opcode

Addressing Mode:

0x = register

10 = memory without index

1x = memory with or without index

11 = memory with index

x_xx_xxxxxxxx_xxx_xxx

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