STMicroelectronics STM32WL5 Series User Manual

Embedded flash memory (FLASH) RM0453
106/1450 RM0453 Rev 5
Note: FLASH_CR and FLASH_C2CR cannot be written when BSY is set respectively in
FLASH_SR or FLASH_C2SR. Any attempt to write to these registers with BSY set causes
the AHB bus to stall until BSY is cleared.
4.3.7 Flash main memory erase sequences
The flash memory erase operation can be performed at page level (page erase) or on the
whole memory (mass erase). Mass erase does not affect the information block (system
flash memory, OTP and option bytes).
Flash memory page erase
The CPU1 is only able to page erase the non-secure part of the user flash memory.
The secure CPU2 is able to page erase both the secure and non-secure parts of the user
flash memory.
A page erase only starts when allowed by PESD in FLASH_SR and FLASH_C2SR.
When a page is protected by PCROP or WRP, it is not erased. Hide protection area and
hide protection area disable provide no protection for erase. A hide protection area when not
protected by PCROP or WRP, can be erased.
To erase a 2-Kbyte page, follow the steps detailed below:
1. Check that no flash memory operation is ongoing by checking BSY in FLASH_SR or
FLASH_C2SR.
2. Check that flash program and erase operation is allowed by checking PESD in
FLASH_SR or FLASH_C2SR (these checks are recommended even if status may
change due to flash operation requests by the other CPU, to limit the risk of receiving a
bus error when starting page erase).
Table 13. Page erase overview
Page
PCROP WRP
PCROP
_RDP
Comment WRPERR
CPU1
bus
error
CPU2
bus
error
Illegal
access
event
Non-secure
No No
x
Page is erased No
No No
No
No Yes
Page erase aborted (no page erase started) YesYes No
Yes Yes
Secure
No No
Requested by CPU2. Secure page is
erased.
No
N/A No
Requested by CPU1. Secure page erase is
aborted (no secure page erase started)
No N/A
Yes
(1)
No Yes
Page erase aborted (no page erase started) Yes
(2)
No NoYes No
Yes Yes
1. When PER requested by the non-secure CPU1.
2. When requested by a secure bus master. When requested by a non-secure bus master, no WRPERR is generated and an
illegal access event is generated instead.

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English