Reset and clock control (RCC) RM0453
292/1450 RM0453 Rev 5
HSE32 is controlled from the CPUs and from the sub-GHz radio (see Section 5: Sub-GHz
radio (SUBGHZ)).
HSE32 can be switched on and off using the HSEON bit in the RCC clock control register
(RCC_CR). The HSE32 clock sources can be either an external crystal (XTAL) or an
external source including a temperature compensated crystal oscillator (TCXO). HSE32
must be enabled with the HSEON bit when used for the CPUs.
The stability of the XTAL HSE32 clock may be impacted by the sub-GHz radio, depending
on the transmit output power (max +22 dBm), heating up the device. Heating depends on
the used transmit output power and the device package. Careful PCB design using thermal
heat dissipation techniques must be applied to avoid heat transfer to the HSE32 reference
clock source. For the HSE32 frequency drift requirements related to the sub-GHz radio, see
Section 5.5.1: LoRa modem.
The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the HSE32
oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the RCC clock interrupt enable register
(RCC_CIER).
The sub-GHz radio enables HSE32 autonomously for its own purpose, independently of the
HSEON bit.
Warning: The HSE32 cannot be used in LPRun mode.
Figure 28. HSE32 clock sources
External crystal (HSE32 crystal)
The associated hardware configuration is shown in Figure 28: HSE32 clock sources. Refer
to the electrical characteristics section of the datasheet for more details.
MSv62606V2
OSC_IN OSC_OUT
tunable load
capacitors
Crystal
External
OSC_IN
OSC_OUT
External
clock source
Not
connected
TCXO
OSC_IN OSC_OUT
Not connected
VDDTCXO
TCXO
Clock source Hardware configuration
C
LIN
C
LOUT
R
CC
C
LIN
Note: Force SUBGHZ_HSEINTRIMR = 0x00
to get C
LIN
= 11.3 pF.
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