RM0453 Rev 5 209/1450
RM0453 Sub-GHz radio (SUBGHZ)
227
5.10.6 Sub-GHz radio frame limit LSB register
(SUBGHZ_RAM_FRAMELIML)
Address offset: 0x0F5
Reset value: 0x00
5.10.7 Sub-GHz radio generic bit synchronization register
(SUBGHZ_GBSYNCR)
Address offset: 0x6AC
Reset value: 0x00
This register must be cleared to 0x00 when using packet types other than LoRa.
5.10.8 Sub-GHz radio generic CFO MSB register (SUBGHZ_GCFORH)
Address offset: 0x6B0
Reset value: 0x00
76543210
FRAMELIML[7:0]
rw rw rw rw rw rw rw rw
Bits 7:0 FRAMELIML[7:0]: frame limit LSB bits
76543210
Res. SBITSYNCEN RXDINV BITSYNCDIS Res. Res. Res. Res.
rw rw rw
Bit 7 Reserved, must be kept at reset value.
Bit 6 SBITSYNCEN: LoRa simple bit synchronization enable
This bit must be cleared to 0 when using generic packet and BPSK type.
0: simple bit synchronization disabled
1: simple bit synchronization enabled
Bit 5 RXDINV: LoRa receive data inversion
This bit must be cleared to 0 when using generic packet and BPSK type.
0: receive data not inverted
1: receive data inverted
Bit 4 BITSYNCDIS: LoRa normal bit synchronization enable
This bit must be cleared to 0 when using generic packet and BPSK type.
0: normal bit synchronization enabled
1: normal bit synchronization disabled
Bits 3:0 Reserved, must be kept at reset value.
76543210
Res Res Res Res DEMOD_CFO[3:0]
rrrr
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