Memory and bus architecture RM0453
66/1450 RM0453 Rev 5
CPU2 system flash boot
CPU2 system flash memory SFI/RSS boot can be selected via BOOT0 and BOOT1.
If, after a reset, the user options are not valid and BOOT0/BOOT1 select CPU1 to boot from
the main flash memory, CPU2 boots instead from the system flash memory SFI/RSS.
Note: When Engi bytes are not valid, or PKA or AES is not available in the product, the SFI/RSS
boot firmware install is not available.
2.4 SRAM erase
SRAM1, SRAM2 and PKA SRAM provide an SRAM erase feature.
These SRAMs are erased under the conditions detailed in the table below.
2.5 Memory protection
System memory protection (security, privilege, and hide protection) is only available when
the system is secure (ESE = 1).
Flash memory, SRAM1 and SRAM2 can be protected by security and privilege at system
level in addition to any privilege protection in the CPUs MPU. Security is defined in flash
memory user options and privilege is defined in GTZC_TZSC registers.
The security and privilege definition protects the memory areas from being accessed by any
non authorized bus master.
Table 2. SRAM erase conditions
Condition SRAM1
(1)
SRAM2
(1)
PKA SRAM
(2)
System reset
(3)
(user option SRAM_RST = 1) Retained Retained Hardware erased
System reset (user option SRAM_RST = 0) Hardware erased Hardware erased Hardware erased
OBL with invalid user options Hardware erased Hardware erased Hardware erased
RDP regression from 1 to 0, on OPTSTRT. Hardware erased
(4)
Hardware erased Hardware erased
Tamper
(5)
Retained Hardware erased Hardware erased
SYSCFG_SCSR SRAM2ER Retained Hardware erased Retained
1. An ongoing SRAM1 or SRAM2 erase can be monitored by SYSCFG_SCSR.SRAMBSY flag.
2. An ongoing PKA SRAM erase can be monitored by SYSCFG_SCSR.PKASRAMBSY flag.
3. POR, NRST, and wake-up from Standby.
4. For more details, see Table 19: RDP regression from level 1 to level 0 and memory erase.
5. To be able to debug without SRAM erase on tamper, especially ITAM6 debug access, the tamper erase must be disabled in
the TAMP by firmware.
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