Power control (PWR) RM0453
280/1450 RM0453 Rev 5
6.6.19 PWR extended status and status clear register (PWR_EXTSCR)
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x088
Reset value: 0x0000 0000
Bit 10 APC: Apply pull-up and pull-down configuration for CPU2
When this bit for CPU2, and the PWR_CR3.APC bit for CPU1, are set, the I/O pull-up and
pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are
applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not
applied to the I/Os.
Bit 9 Reserved, must be kept at reset value.
Bit 8 EWPVD: PVD and wake-up for CPU2 enable (when sub-GHz radio is in active state)
This bit is set and reset by software.
When this bit is set, PVD is enabled while the sub-GHz radio is active and triggers an
interrupt and wake-up from Standby event to CPU2, when the voltage level drops below the
PVD threshold level.
0: PVD not enabled by the sub-GHz radio active state
1: PVD enabled while the sub-GHz radio is active
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 EWUP3: Enable wake-up pin WKUP3 for CPU2
When this bit is set, the external wake-up pin WKUP3 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event to CPU2 when a rising or a falling edge
occurs. The active edge is configured via the WP3 bit in the PWR control register 4
(PWR_CR4).
Bit 1 EWUP2: Wake-up pin WKUP2 for CPU2 enable
When this bit is set, the external wake-up pin WKUP2 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event to CPU2 when a rising or a falling edge
occurs . The active edge is configured via the WP2 bit in the PWR control register 4
(PWR_CR4).
Bit 0 EWUP1: Wake-up pin WKUP1 for CPU2 enable
When this bit is set, the external wake-up pin WKUP1 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event to CPU2 when a rising or a falling edge
occurs. The active edge is configured via the WP1 bit in the PWR control register 4
(PWR_CR4).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
C2DS C1DS
C2STO
PF
C2STO
P2F
C2SBF
C1STO
PF
C1STO
P2F
C1SBF Res. Res. Res. Res. Res. Res.
C2CSS
F
C1CSS
F
rrrrrrrr ww
Bits 31:16 Reserved, must be kept at reset value.
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