Embedded flash memory (FLASH) RM0453
144/1450 RM0453 Rev 5
4.10.15 FLASH IPCC mailbox data buffer address register
(FLASH_IPCCBR)
Address offset: 0x03C
Reset value: 0xFFFF FFFF
Default reset value from ST production is given. Subsequently, 0b1111 1111 1111 1111 11XX
XXXX XXXX XXXX, the option bits are loaded with user values from the flash memory at
power-on reset release.
This register can only be written by CPU1 in RDP level 0 or RDP level 1.
When the system is secure (ESE = 1), this register is further more protected by the
PRIVMODE. When privilege protection is enabled in PRIVMODE, this register provides
write access privilege and can only be written by a privileged access. Unprivileged write
access is ignored and an illegal access event is generated. Unprivileged read access is still
allowed.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. PCROP1B_END[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1B_END[7:0]: PCROP1B area end offset
Contains the first 1-Kbyte page of the PCROP1B area.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. IPCCDBA[13:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 IPCCDBA[13:0]: IPCC mailbox data buffer base address offset
IPCCDBA can be used by software to indicate the IPCC buffer structure base address.
Definition and resolution is fully under software control.
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