RM0453 Rev 5 457/1450
RM0453 Direct memory access controller (DMA)
479
The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates a secure bus and a privileged bus, to keep the DMAMUX
peripheral informed of the secure or non-secure state, and the privileged or unprivileged
state of each channel x.
The DMA controller generates an interrupt per channel to the interrupt controller.
The DMA controller also generates an illegal access event, as a pulse, to the secure
interrupt controller, when a non-secure software attempts to access a secure DMA register
or register field.
13.4.2 DMA pins and internal signals
13.4.3 DMA transfers
The secure software configures the DMA controller at channel level, in order to perform a
block transfer, composed of a sequence of AHB secure or non-secure, privileged or
unprivileged bus transfers.
A DMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.
After an event, the following steps of a single DMA transfer occur:
1. The peripheral sends a single DMA request signal to the DMA controller.
2. The DMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the DMA controller.
4. The peripheral releases its request as soon as it gets the acknowledge from the DMA
controller.
5. Once the request is de-asserted by the peripheral, the DMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single DMA transfer.
Table 78. DMA internal input/output signals
Signal name Signal type Description
dma_req[x] Input DMA channel x request
dma_ack[x] Output DMA channel x acknowledge
dma_it[x] Output DMA channel x interrupt
dma_secm[x] Output DMA channel x secure state
dma_priv[x] Output DMA channel x privileged state
dma_ilac Output DMA global secure/privileged illegal access event
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