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RM0453 Rev 5 857/1450

RM0453 General-purpose timer (TIM2)

892

26.3.18 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset

mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.

Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is

generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.

In the following example, the upcounter is cleared in response to a rising edge on TI1 input:

1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

(in this example, we do not need any filter, so we keep IC1F=0000). The capture

prescaler is not used for triggering, so it does not need to be configured. The CC1S bits

select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write

CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect

rising edges only).

2. Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select

TI1 as the input source by writing TS=00101 in TIMx_SMCR register.

3. Start the counter by writing CEN=1 in the TIMx_CR1 register.

The counter starts counting on the internal clock, then behaves normally until TI1 rising

edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the

trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if

enabled (depending on the TIE bit in TIMx_DIER register).

The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the

resynchronization circuit on TI1 input.

Figure 227. Control circuit in reset mode

Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when TI1 input is low:

MS31401V2

Counter clock = ck_cnt = ck_psc

Counter register

01 02 03 00 01 02 0332 33 34 35 36

TI1

3130

TIF

STMicroelectronics STM32WL5 Series User Manual

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