RM0453 Rev 5 1281/1450
RM0453 Serial peripheral interface / integrated interchip sound (SPI/I2S)
1311
37.7 I2S functional description
37.7.1 I2S general description
The block diagram of the I2S is shown in Figure 363.
Figure 363. I2S block diagram
1. MCK is mapped on the MISO pin.
The SPI can function as an audio I2S interface when the I2S capability is enabled (by
setting the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same
pins, flags and interrupts as the SPI.
Tx buffer
Shift register
16-bit
Communication
Rx buffer
16-bit
MOSI/SD
Master control logic
MISO
SPI
baud rate generator
I2SMOD
LSB first
LSB
First
SPE BR2 BR1 BR0 MSTR
CPOL CPHA
Bidi
mode
Bidi
OE
CRC
EN
CRC
Next
DFF
Rx
only
SSM
SSI
Address and data bus
control
NSS/WS
BSY OVR MODF
CRC
ERR
CH
SIDE
TxE RxNE
I
2
S clock generator
MCK
I2S_
CK
I2S
MOD
I2SE
CH
DATLEN
LEN
CK
POL
I2SCFG
I2SSTD
MCKOE ODD I2SDIV[7:0]
[1:0]
[1:0]
[1:0]
UDR
I2SxCLK
MS32126V1
FRE
CK
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