RM0453 Rev 5 971/1450
RM0453 Low-power timer (LPTIM)
972
28.7.12 LPTIM repetition register (LPTIM_RCR)
Address offset: 0x028
Reset value: 0x0000 0000
Caution: The LPTIM_RCR register must only be modified when the LPTIM is enabled (ENABLE bit
set to ‘1’). When using repetition counter with PRELOAD = 0, LPTIM_RCR register must be
changed at least five counter cycles before the auto reload match event, otherwise an
unpredictable behavior may occur.
28.7.13 LPTIM register map
The following table summarizes the LPTIM registers.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 REP[7:0]: Repetition register value
REP is the repetition value for the LPTIM.
Table 203. LPTIM register map and reset values
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
LPTIM_ISR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REPOK
UE
DOWN
(1)
UP
(1)
ARROK
CMPOK
EXTTRIG
ARRM
CMPM
Reset value
000000000
0x004
LPTIM_ICR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REPOKCF
UECF
DOWNCF
(1)
UPCF
(1)
ARROKCF
CMPOKCF
EXTTRIGCF
ARRMCF
CMPMCF
Reset value
000000000
0x008
LPTIM_IER
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REPOKIE
UEIE
DOWNIE
(1)
UPIE
(1)
ARROKIE
CMPOKIE
EXTTRIGIE
ARRMIE
CMPMIE
Reset value
000000000
0x00C
LPTIM_CFGR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ENC
(1)
COUNTMODE
PRELOAD
WAVPOL
WAVE
TIMOUT
TRIGEN
Res.
TRIGSEL[2:0]
Res.
PRESC
Res.
TRGFLT
Res.
CKFLT
CKPOL
CKSEL
Reset value
00000000 000 000 00 00000
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