RM0453 Rev 5 1289/1450
RM0453 Serial peripheral interface / integrated interchip sound (SPI/I2S)
1311
Figure 380. PCM standard waveforms (16-bit extended to 32-bit packet frame)
Note: For both modes (master and slave) and for both synchronizations (short and long), the
number of bits between two consecutive pieces of data (and so two synchronization signals)
needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in
slave mode.
37.7.3 Start-up description
TheFigure 381 shows how the serial interface is handled in MASTER mode, when the
SPI/I2S is enabled (via I2SE bit). It shows as well the effect of CKPOL on the generated
signals.
MS30107V1
CK
WS
short frame
SD
WS
long frame
Up to 13-bits
MSB
LSB
16 bits
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