STMicroelectronics STM32WL5 Series - Memory and Bus Architecture; System Architecture

RM0453 Rev 5 61/1450
RM0453 Memory and bus architecture
70
2 Memory and bus architecture
The following definitions are used in this section:
• CPU1 = Arm Cortex-M4 with MPU and DSP
• CPU2 = Arm Cortex-M0+ with MPU
When ESE = 0, CPU2 is non-secure. When ESE = 1, CPU2 is secure.
2.1 System architecture
The main system consists of a 32-bit multilayer AHB bus matrix that interconnects the
following masters and slaves:
• Six masters:
– CPU1 core I-bus
– CPU1 core D-bus
– CPU1 core S-bus
– CPU2 core S-bus
–DMA1
–DMA2
• Eight slaves:
– Internal flash memory on the CPU1 Code bus
– Internal flash memory on CPU1 DCode bus
– Internal flash memory on CPU2 S bus
– Internal SRAM1 (32 Kbytes)
– Internal SRAM2 (32 Kbytes)
– AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
– AHB2 peripherals
– AHB3 peripherals including AHB to APB bridges and APB peripherals (connected
to APB3)
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously.