RM0453 Rev 5 1405/1450
RM0453 Debug support (DBG)
1435
38.11.19 TPIU CoreSight component identity register 2 (TPIU_CIDR2)
Address offset: 0xFF8
Reset value: 0x0000 0005
38.11.20 TPIU CoreSight component identity register 3 (TPIU_CIDR3)
Address offset: 0xFFC
Reset value: 0x0000 00B1
38.11.21 CPU 1 TPIU register map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[19:12]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. PREAMBLE[27:20]
rrrrrrrr
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[27:20]: component ID bits [31:24]
0xB1: Common ID value
Table 281. TPIU register map and reset values
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
TPIU_SSPSR PORTSIZE[31:0]
Reset value 00000000000000000000000000001111
0x004
TPIU_CSPSR PORTSIZE[31:0]
Reset value 00000000000000000000000000000001
0x008 to
0x00C
Reserved Reserved.
0x010
TPIU_ACPR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PRESCALER[12:0]
Reset value 0000000000000
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