STMicroelectronics STM32WL5 Series - Figure 145. Counter Timing Diagram, Internal Clock Divided by N; Figure 146. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)

Advanced-control timer (TIM1) RM0453
736/1450 RM0453 Rev 5
Figure 145. Counter timing diagram, internal clock divided by N
Figure 146. Counter timing diagram, update event with ARPE=1 (counter underflow)
00
1F
20
MS31192V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
01
FD 36
MS31193V1
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
00 02 03 04 05 06 0701
CEN
Auto-reload preload
register
Write a new value in TIMx_ARR
06 05 04 03 02 01
FD 36
Auto-reload active
register