Reset and clock control (RCC) RM0453
296/1450 RM0453 Rev 5
The PLLQCLK and PLLRCLK output frequency must not exceed 48 MHz. The PLLPCLK
output frequency must not exceed 62 MHz.
The enable bits of the PLL output clock (PLLPEN, PLLQEN, PLLREN) can be modified at
any time without stopping the PLL. PLLREN cannot be cleared if PLLRCLK is used as
system clock.
7.2.5 LSE clock
The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It provides
a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for
clock/calendar or other timing functions.
The resonator and the load capacitors must be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. The loading
capacitance values must be adjusted according to the selected oscillator.
Figure 30. LSE clock sources
The LSE crystal is switched on and off using the LSEON bit in the RCC backup domain
control register (RCC_BDCR). The crystal oscillator driving strength can be changed at
runtime using the LSEDRV[1:0] bits in the RCC backup domain control register
(RCC_BDCR) to obtain the best compromise between robustness and short start-up time
on one side and low-power-consumption on the other side. The LSE drive can be decreased
to the lower drive capability (LSEDRV = 0) when the LSE is on. However, once LSEDRV is
selected, the drive capability can not be increased if LSEON = 1.
The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates
whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not
released until this bit is set by hardware. An interrupt can be generated if enabled in the
RCC clock interrupt enable register (RCC_CIER).
When enabled and ready the LSE clock can directly be used by the RTC. To be able to use
the clocks by other peripherals (LPTIMx, TIMx, USARTx, LPUARTx, system LSCO, MCO,
MSI PLL mode), the LSE system clock must be enabled with the LSESYSEN bit in the RCC
backup domain control register (RCC_BDCR). When the LSE clock is ready and LSECSS is
enabled, the LSE clock is used by the LSECSS and is available on the LSCO. A
LSESYSRDY flag is provided in the RCC backup domain control register (RCC_BDCR) to
indicate when LSE system clock is ready (due clock synchronization) after having been
enabled by the LSESYSEN.
MSv62608V1
OSC32_IN
OSC32_OUT
Load
capacitors
Crystal/
ceramic
resonators
External
OSC32_IN
OSC32_OUT
External
clock source
GPIO
Clock source Hardware configuration
C
L1
C
L2
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